The present invention is directed generally to data communication. More particularly, the present invention relates to methods and arrangements for transferring data over parallel data interconnect circuits and to calibrating and overcoming errors caused by skewed data in transfers between nodes.
Ongoing demands for more-complex circuits have led to significant achievements that have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often designed as functionally-defined blocks that operate on a sequence of data and then pass that data on for further processing. This communication from such functionally-defined blocks can be passed in small or large amounts of data between individual integrated circuits (or xe2x80x9cchipsxe2x80x9d), within the same chip and between more remotely-located communication circuit arrangements and systems. Regardless of the configuration, the communication typically requires closely-controlled interfaces to insure that data integrity is maintained and that chip-set designs are sensitive to practicable limitations in terms of implementation space and available operating power.
With the increased complexity of circuits, there has been a commensurate demand for increasing the speed at which data is passed between the circuit blocks. Many of these high-speed communication applications can be implemented using parallel data interconnect transmission in which multiple data bits are simultaneously sent across parallel communication paths. Such xe2x80x9cparallel bussingxe2x80x9d is a well-accepted approach for achieving data transfers at high data rates. For a given data-transmission rate (sometimes established by a clock passed along with the data), the interconnect bandwidth, measured in bits-per-second, is equivalent to the data transmission rate times the number of data signals comprising the parallel data interconnect.
A typical system might include a number of modules (i.e., one or more cooperatively-functioning chips) that interface to and communicate over a parallel data bus, for example, in the form of a cable, other interconnect and/or via an internal bus on a chip. A transmitting module transmits data over the bus synchronously with a clock on the transmitting module. In this manner, the transitions on the parallel signal lines leave the transmitting module in a synchronous relationship to each other and/or to a clock on the transmitting module. At the other end of the parallel data interconnect, the receiving module receives the data on the parallel data bus; where the interconnect passes a clock signal, the receive clock is typically derived from or is synchronous with clock on the transmitting module. The rate at which the data is passed over the parallel signal lines is sometimes referred to as the (parallel) xe2x80x9cbus rate.xe2x80x9d
In such systems, the received signals (and where applicable the receive clock) should have a specific phase relationship with the transmit clock in order to provide proper data recovery. There is often an anticipated amount of time xe2x80x9cskewxe2x80x9d between the transmitted data signals themselves and between the data signals and the receive clock at the destination. A skew can be caused by a number of phenomena including, for example, transmission delays introduced by the capacitive and inductive loading of the signal lines of the parallel interconnect, variations in the input/output driver source, intersymbol interference and variations in the transmission lines"" impedance and length. Regardless of which phenomena cause the skew, the phenomena present a serious integrity issue for the data being communicated and, in many applications, the overall communication system.
While there have been a number of previous approaches to address this skew issue, many of these approaches have required that the signal path be taken out of service to permit a calibration process to be performed. Moreover, some calibration processes are inefficient and require that the channel be taken out of service for a considerable time. Such xe2x80x9cdowntimexe2x80x9d is often unduly expensive and can be intolerable in some applications.
Accordingly, improving data communication over parallel busses permits more practicable and higher-speed parallel bussing applications which, in turn, can directly lead to serving the demands for high-speed circuits while maintaining data integrity in the presence of skew-causing phenomena. Various aspects of the present invention address the above-mentioned deficiencies and also provide for communication methods and arrangements that are useful for other applications as well.
Various aspects of the present invention are directed to data transfer over parallel-interconnect circuits in a manner that addresses and overcomes the above-mentioned issues. In one example application involving a high-speed data transfer over a parallel data bus, the present invention permits significant increases in the data-transmission rate while maintaining data integrity.
One particular example embodiment of the present invention involves a parallel data communication arrangement in which digital data is transferred in parallel between two communication nodes. The arrangement includes a parallel arrangement of data paths for passing data in parallel between at least two nodes and an additional calibration path for data calibration; and calibration mode circuitry adapted to compare a sequence of data over the calibration path relative to a matched sequence of data being passed on one of the multiple data paths, the calibration mode circuitry also being adapted to adjust a transmission time in response to the comparison
According to another example embodiment of the present invention, the parallel data communication arrangement includes a parallel arrangement of M paths for passing concurrently N bits of data in parallel from a first node to a second node, and an additional calibration path for calibrating the data passed in parallel from the first node to the second node, where M is greater than N. Also included are M data drivers respectively coupled to the M paths at the first node and M data receivers respectively coupled to the M paths at the second node. A calibration circuit compares a sequence of data over a selected one of the M paths relative to a matched sequence of data being passed for one of the N bits of data, and the calibration circuit adjusts a transmission time for the selected one of the M bits of data in response to the comparison.
Another important aspect of the present invention is directed to uses of the above-described data paths, including using the additional calibration path for data calibration, wherein the data paths have rotating assignments during calibration. One, of the data paths, or the additional calibration path, is selected for passing the calibration, data while the other paths are used to pass noncalibration data, and then another of the paths is selected for passing the calibration data while the others are used to pass noncalibration data. This rotation of assignments continues with the transmission time being adjusted in response to each comparison.
A more specific aspect of this rotational-assignment implementation involves performing the comparison between immediately adjacent pairs of the data paths. In this manner, the likelihood of accurately reducing skew is maximized.
Certain other embodiments of the present invention are respectively directed to methods implemented in a manner consistent with the above embodiments, to procedures for rotating the calibration procedure through each of the data paths while using the calibration path as a spare path to maintain communication integrity, and to various embodiments for controlling the calibration procedure and for detecting whether the data is skewed.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description that follow more particularly exemplify these embodiments.